The demand on electronic circuitry to accurately recover serially transmitted digital data has expanded as the speed of such transmissions has increased. High speed transmissions typically become distorted due to timing jitter and other sources of noise which, for all practical purposes, cannot be eliminated. Phase shifting of the serial transmission can also distort the data, especially when the incoming data and the receiving circuitry are not frequency locked to the same local clock. As expected, such distortions can result in data being lost or misread by the receiving circuitry.
In order to accurately track and decipher an incoming data transmission, many circuits currently use a digital phase-locked loop coupled with a delay circuit for reducing the effects of noise and phase shifting. The delay circuit, also referred to as a delay line, provides an output signal which lags by a precise amount with respect to the incoming data transmission for use in reading the data.
Delay lines have many applications. For example, delay lines are commonly used in disc drive systems and high speed dynamic RAM devices, which comprise the main memory of virtually all personal computers.
Delay lines normally consist of a plurality of series-connected cells, such as inverters, that are cascaded together. Each inverter provides a known amount of delay for delaying a digital signal consisting of data or control signals, to produce a delayed, or phase shifted copy of the original signal. The total amount of delay provided by the delay line is controlled by feedback from the phase-locked loop tracking the digital signal. Correspondingly, the output of the delay line provides a clock pulse with the appropriate phase to read the incoming data, enable signal synchronization, or other similar tasks.
Circuits which use delay lines typically require a fixed clock running at approximately the bit rate of the data to be recovered. However, even with the bit rate being known, problems arise when a frequency difference develops between the data frequency and the clock being used by the data recovery circuitry.
For instance, if the data frequency is slightly lower than the frequency used by the recovery circuitry, many of the prior art data recovery circuits will detect the phase drift and increase the amount of delay provided by the delay line such that the delay line output tracks (i.e., remains in phase with) the data frequency. This process of adjusting the phase used by the recovery circuitry will continue as both the data keeps arriving and the delay line is capable of increasing the amount of delay.
In theory, if the data transmission is infinitely long, then the delay line would need to be infinitely long to phase shift the recovery circuitry in the same direction as the incoming data. This would allow the recovery circuitry to track the incoming data for an infinite length of time. Further, it would give the recovery circuitry an infinite phase range. However, equipping recovery circuitry with a delay line of infinite length is not realistic.
U.S. Pat. No. 5,451,894, issued to Guo, provides a digital full range rotating phase shifter for use in controlled phase shifting, signal synchronization and data recovery. The phase shifter includes a rotating phase shift control and a phase shift range calibrator for increasing and decreasing the delay provided by a digitally adjustable delay. The disclosed device will "wrap around" the delay generated by the adjustable delay circuitry so that bidirectional 360 degree phase rotation is provided. The device requires, however, an array of complex control logic that can contribute to the generation of noise to surrounding circuitry.
The present invention overcomes the above discussed problems by providing an efficient circuit design with infinite linear phase adjustability and very long hold time for recovering serially transmitted digital signals.